A thermoelectric generator (TEG) converts body heat into electricity to supply power to sensors. However, the output voltage of a TEG is usually very low (often a few hundred millivolt or less). Therefore, a TEG requires a low-voltage high-efficiency voltage converter.
Usually, this is achieved by using an inductive direct current-to-direct current (DC-DC) converter, supported by a start-up circuit. The start-up circuit must be able to start-up by itself and generate a sufficiently high voltage for the control circuits of the inductive DC-DC converter to operate. This start-up circuit is very often a capacitive charge-pump circuit. An alternative method would be to omit the inductive DC-DC converter and to perform all the power transfer by using the capacitive charge-pump circuit, and not only during start-up.
“An experimental 1.5V 64 Mb DRAM” by Y. Nakagome, H. Tanaka, et al., IEEE J. Solid-State Circuits, vol. 26, no. 4, pp. 465-472, April 1991 describes a basic voltage-doubler as used in many charge pump circuits.
FIG. 1 illustrates a known charge pump circuit implemented using voltage doubler circuits. The charge-pump circuit 10 of FIG. 1, seen from down to up, comprises a series circuit of first voltage doubler circuit 1, a second voltage doubler circuit 2, and a third voltage doubler circuit 3.
The charge pump circuit 10 of FIG. 1 comprises a plurality of transistors Ti (i=1, 2, . . . , 12). Each one of these transistors Ti has a respective gate Gi, a source Si, and a drain Di. For the sake of simplicity, a transistor Ti will be called an ith transistor in the specification hereinafter. The charge pump circuit 10 of FIG. 1 also comprises a plurality of capacitors Cj (j=1, 2, . . . , 6). Each one of these capacitors Cj has a first end cj1 and a second end cj2. It is observed that the reference number concerned may be different in the claims, as they may appear in another order in the claims.
FIG. 1, also shows the voltage received and delivered by each of the voltage doubler circuits: the first voltage doubler circuit 1 is arranged to receive a voltage Vin1 from the input Vin of the charge pump circuit 10 and to deliver a voltage Vout1 to the second voltage doubler circuit 2, the second voltage doubler circuit 2 is arranged to receive a voltage Vin2 and to deliver a voltage Vout2 to the third voltage doubler circuit 3, and the third voltage doubler circuit 3 is arranged to receive a voltage Vin3 and to deliver a voltage Vout3 to the output Vout of the charge pump circuit 10 of FIG. 1.
The charge pump circuit 10 of FIG. 1 comprises a first clock signal generator CLKp and a second clock signal generator CLKn. The first clock signal generator CLKp is configured to generate a first clock signal and the a second clock signal generator CLKn is configured to generate a second clock signal, wherein the second clock signal is low when the first clock signal is high and the second clock signal is high when the first clock signal is low.
The charge pump circuit 10 of FIG. 1 comprises a capacitor Cout having a first end cout1 and a second end cout2. The first end cout1 of Cout is connected to the output Vout of the charge pump circuit 10 of FIG. 1. The second end cout2 of Cout is connected to the ground.
The first voltage doubler circuit of the charge pump circuit 10 of FIG. 1 includes a first N-type metal oxide semiconductor transistor (NMOST) T1, a second N-type metal oxide semiconductor transistor T2, a third P-type metal oxide semiconductor transistor (PMOST) T3, and a fourth P-type metal oxide semiconductor transistor T4. The first voltage doubler circuit of the charge pump circuit 10 of FIG. 1 also includes a first capacitor C1 having a first end c11 and a second end c12 and a second capacitor C2 having a first end c21 and a second end c22. The first NMOST T1 and the second NMOST T2 have their source terminals S1 and S2 connected to the input Vin of the charge pump circuit and their drain terminals D1 and D2 are connected respectively to the second end c12 of capacitor C1 and to the first end c21 of capacitor C2. The drain terminal D1 of the first NMOST T1 is also connected to the drain terminal D3 of the third PMOST T3, to the gate terminal G4 of fourth PMOST T4 and to the gate terminal G2 of second NMOST T2. The drain terminal D2 of the second NMOST T2 is also connected to the drain terminal D4 of the fourth PMOST T4, to the gate terminal G3 of third PMOST T3 and to the gate terminal G1 of first NMOST T1, The third PMOST T3 and the fourth PMOST T4 have their source terminals S3 and S4 connected to the output of the first double voltage circuit.
The output Vout1 of the first double voltage circuit 1 of the charge pump circuit 10 of FIG. 1 is connected to the input of the second voltage doubler circuit of the charge pump circuit.
The second voltage doubler circuit of the charge pump circuit 10 of FIG. 1 includes a fifth NMOST T5, a sixth NMOST T6, a seventh PMOST T7, and an eighth PMOST T8. The second voltage doubler circuit of the charge pump circuit 10 of FIG. 1 also includes a third capacitor C3 having a first end c31 and a second end c32 and a fourth capacitor C4 having a first end c41 and a second end c42. The fifth NMOST T5 and the sixth NMOST T6 have their source terminals S5 and S6 connected to the input Vin2 of the second voltage doubler circuit 2 of the charge pump circuit 10 of FIG. 1, and their drain terminals D5 and D6 connected respectively to the second end c32 of capacitor C3 and to the first end c41 of capacitor C4. The drain terminal D5 of the fifth NMOST T5 is also connected to the drain terminal D7 of the seventh PMOST T7, to the gate terminal G8 of eighth PMOST T8 and to the gate terminal G6 of sixth NMOST T6. The drain terminal D6 of the sixth NMOST T6 is also connected to the drain terminal D8 of the eighth PMOST T8, to the gate terminal G7 of seventh PMOST T7 and to the gate terminal G5 of fifth NMOST T5. The seventh PMOST T7 and the eighth PMOST T8 have their source terminals S7 and S8 connected to the output Vout2 of the second double voltage circuit 2.
The output Vout2 of the second double voltage circuit 2 of the charge pump circuit 10 of FIG. 1 is connected to the input Vin3 of the third voltage doubler circuit 3 of the charge pump circuit 10.
The third voltage doubler circuit 3 of the charge pump circuit 10 of FIG. 1 includes a ninth NMOST T9, a tenth NMOST T10, a eleventh PMOST T11, and a twelfth PMOST T12. The third voltage doubler circuit of the charge pump circuit 10 of FIG. 1 also includes a fifth capacitor C5 having a first end c51 and a second end c52 and a sixth capacitor C6 having a first end c61 and a second end c62. The ninth NMOST T9 and the tenth NMOST T10 have their source terminals S9 and S10 connected to the input of the third voltage doubler circuit of the charge pump circuit 10 of FIG. 1, and their drain terminals D9 and D10 connected respectively to the second end c52 of capacitor C5 and to the first end c61 of capacitor C6. The drain terminal D9 of the ninth NMOST T9 is also connected to the drain terminal D11 of the eleventh PMOST T11, to the gate terminal G12 of twelfth PMOST T12 and to the gate terminal G10 of tenth NMOST T10. The drain terminal D10 of the tenth NMOST T10 is also connected to the drain terminal D12 of the twelfth PMOST T12, to the gate terminal G11 of eleventh PMOST T11 and to the gate terminal G9 of ninth NMOST T9 The eleventh PMOST T11 and the twelfth PMOST T12 have their source terminals S11 and S12 connected to the output Vout3 of the third double voltage circuit 3.
The output Vout3 of the third double voltage circuit 3 of the charge pump circuit 10 of FIG. 1 is connected to the output Vout of the charge pump circuit 10.
The first clock signal generator CLKp of the charge pump circuit 10 of FIG. 1 is connected to the first end c11 of capacitor C1, to the first end c31 of capacitor C3, and to the first end c51 of capacitor C5. The second clock signal generator CLKn of the charge pump circuit 10 of FIG. 1 is connected to the second end c22 of capacitor C2, to the second end c42 of capacitor C4, and to the second end c62 of capacitor C6.
Now it will be explained how the charge pump circuit 10 of FIG. 1 works.
The first clock signal generator CLKp of the charge pump circuit 10 of FIG. 1 oscillates between a low value of zero and a high value of VDD. The second clock signal generator CLKn of the charge pump circuit 10 of FIG. 1 oscillates between a high value of VDD and a low value of zero.
In phase 1, the first clock signal generator CLKp is low, the second clock signal CLKn is high, the first NMOST T1 and the fourth transistor PMOST T4 are conducting while the second NMOST T2 and the third transistor PMOST T3 are in cut-off. The capacitor C1 is charging to the input voltage Vin1. In phase 2, the first clock signal generator CLKp is high, the second clock signal CLKn is low, the first NMOST T1 and the fourth transistor PMOST T4 are in cut-off while the second NMOST T2 and the third transistor PMOST T3 are conducting, therefore the charge Vin1 of the capacitor C1 is transferred partially to the output Vout1 to keep the output voltage higher than the input voltage Vin1. The capacitor C2 does the same but in opposite phases, i.e., in phase 1 its charge is transferred partially to the output Vout1 and in phase 2 the capacitor C2 is charging to the input voltage Vin1. By cascading several voltage doubling stages, an output voltage Vout higher than the input voltage Vin can be obtained, as each double voltage circuit provides a higher input voltage to the following double voltage circuit.
In the basic voltage-doubler implemented in FIG. 1, the transistors are turned-on with an absolute gate-source voltage VGS of not more than Vin=VDD (assuming that the clock signals are both toggling between 0V and VDD, and assuming that the output is equal to twice Vin, which is the intended operation).
This limited voltage to turn-on the transistors has a negative effect on the drive capability of the circuit and the minimum input voltage Vin at which the circuit can operate.